`timescale 1ns / 1ps

module seq( 
input clk,  
input i_data,//输入信号 
input valid,//输入信号有效 
input rst_n, //系统复位，低电平有效 
output result//有效序列输出 
); 

reg [5:0] data_list = 6'b000_000;

assign result = (data_list == 6'b111_000 || data_list == 6'b101_110)?1:0;

//控制data_list读入
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
        data_list <= 6'b000_000;
    end
    else begin
        if(valid) 
            data_list <= {data_list[4:0],i_data};
        else
            data_list <= data_list;
    end
end

endmodule
